General phase locked loops (PLL) are designed on the assumption that a signal comprising a stream of evenly spaced pulses is input thereto. Therefore, a frequency-divided signal of such an input signal also has a regular pulse-to-pulse interval.
On the other hand, some PLLs receive, as an input signal, a signal with gaps in the sequence of pulses. Such a PLL outputs, for example, pulses with the same wavenumber as that of the pulses of the input signal with gaps, at equally-spaced phase intervals. The PLL is configured to set, for example, its loop bandwidth low to thereby filter out the effect of phase jumps due to the pulse gaps of the input signal, and then output pulses with the same wavenumber as that of the input pulses at equally-spaced phase intervals.
Note that some conventional PLLs having been proposed prevent malfunction due to interruption of a reference clock (see, for example, Japanese Laid-open Patent Publication No. 09-51267).
However, the conventional PLLs employ the method of reducing the loop bandwidth, which leaves a problem of poor tracking performance (response) of the output signal to changes in the input signal.